This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-199841, filed Jun. 30, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to the structure of a collector region of a vertical bipolar transistor.
2. Description of the Related Art
There is a trade-off relationship between the characteristics of the bipolar transistor, such as withstanding voltage and capacitance, and design parameters for designing the bipolar transistor. It is thus important to adopt a technique of optimizing the design parameters and designing the bipolar transistor faithfully to the design parameters.
A prior art vertical bipolar transistor will now be described with reference to FIG. 1. FIG. 1 is a cross-sectional view of a pnp bipolar transistor.
As FIG. 1 shows, a p+-type buried layer 110, which serves as a collector region, is formed in an n-type silicon substrate 100. A pxe2x88x92-type epitaxial silicon layer 120 is formed on the surface of the substrate 100. The layer 120 serves as a collector region whose concentration is lower than that of the p+-type buried layer 110. An n-type diffusion layer 130, which serves as a base region, is formed in a surface area of the layer 120. A p+-type diffusion layer 140, which serves as an emitter region, is formed in a surface area of the layer 130. Furthermore, two p+-type diffusion layers 150, which contact the p+-type buried layer 110, are formed in the pxe2x88x92type epitaxial silicon layer 120. The bipolar transistor is thus obtained as described above.
In the above prior art vertical bipolar transistor, a collector-to-emitter saturation voltage lowers (the impedance of the collector region lowers) without decreasing a withstanding voltage. Therefore, the collector region has a two-layer structure of the layer 110 doped with impurities to make the concentration relatively high and the layer 120 doped with impurities to make the concentration lower than that of the layer 110.
When the bipolar transistor performs a normal operation, a reversed bias is applied to a pn junction between the base and collector regions. In the above bipolar transistor, the impurity concentration of the collector region 120 is lower than that of the base region 130, so that most part of a depletion layer 160 formed at the pn junction is included in the collector region 120. The base-to-collector parasitic capacitance almost depends upon the depletion layer formed in the collector region 120. Usually, the width (thickness) DC of the collector region 120 is set greater than that Wc of the depletion layer formed in the collector region 120 by an applied voltage in the normal operation.
As described above, the base-to-collector parasitic capacitance in the prior art bipolar transistor depends upon the depletion layer formed in the collector region 120 doped with impurities to make the concentration of the collector region relatively low. The depletion layer is formed widely and thus the parasitic capacitance is limited to a relatively small value.
Since, however, the impurity concentration of the collector region 120 is low, the dependence of the width of the depletion layer upon the applied voltage increases. In other words, the width of the depletion layer is greatly varied with a voltage applied between the base and collector, as is the parasitic capacitance. When an oscillation circuit is formed using such a bipolar transistor, the base-to-collector parasitic capacitance is greatly changed with the applied voltage, and thus the oscillation frequency of the oscillation circuit is widely varied (pushing).
The collector region of the prior art vertical bipolar transistor has the two-layer structure described above. The structure includes the collector region 110 doped with impurities to make the concentration of the region 110 high and the collector region 120 doped with impurities to make the concentration of the region 120 low and connected to the base region. The low-impurity-concentration collector region 120 is formed more widely than the depletion layer generated by the voltage applied in the normal operation and most of the region 120 is formed in the collector region due to a difference in impurity concentration. The base-to-collector parasitic capacitance therefore depends upon the depletion layer formed in the low-impurity-concentration collector region 120, and the depletion layer is formed widely. The parasitic capacitance is limited to a relatively small value. However, the width of the depletion layer is widely varied with the voltage applied between the base and collector and thus the parasitic capacitance varies greatly. Further, when an oscillation circuit is formed using the above prior art bipolar transistor, the base-to-collector parasitic capacitance is greatly changed with the applied voltage and thus the parasitic capacitance is greatly varied, with the result that the oscillation frequency of the oscillation circuit is widely varied.
The present invention has been developed in consideration of the above situation and an object thereof is to provide a semiconductor device capable of suppressing variations of the width of a depletion layer due to an applied voltage while reducing the parasitic capacitance at a pn junction.
In order to attain the above object, a semiconductor device according to a first aspect of the present invention comprises a first semiconductor region of a first conductivity type, the first semiconductor region serving as a collector region; a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region and serving as a collector region whose impurity concentration is lower than that of the first semiconductor region; a third semiconductor region of a second conductivity type, the third semiconductor region being provided in the second semiconductor region and serving as a base region; and a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided in the third semiconductor region and serving as an emitter region, wherein the second semiconductor region is thinner than a depletion layer formed in the collector region when a potential difference between the base region and the emitter region is substantially equal to a potential difference between the collector region and the emitter region.
According to the semiconductor device so constituted, a base-to-emitter voltage Vbe is almost equal to a collector-to-emitter voltage Vce in a bipolar transistor including a high-impurity-concentration region and a low-impurity-concentration region contacting the base region. In other words, the low-impurity-concentration region is set thinner than a depletion layer formed in the collector region when the base-to-collector voltage Vbc is almost OV. In the bipolar transistor that operates on the condition that the base-to-collector voltage Vbc is almost OV, the variation of the depletion layer when a reversed bias is applied between the base and collector can be reduced and so can be that of parasitic capacitance generated between the base and collector in the normal operation, keeping the parasitic capacitance at the same level as that of the prior art. If an oscillation circuit is constituted of the bipolar transistor, the variation of oscillation frequency of the oscillation circuit can be suppressed and the operation reliability of the oscillation circuit can be improved.
A semiconductor device according to a second aspect of the present invention comprises a first semiconductor region of a first conductivity type, the first semiconductor region serving as a collector region; a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region and serving as a collector region whose impurity concentration is lower than that of the first semiconductor region; a third semiconductor region of a second conductivity type, the third semiconductor region being provided in the second semiconductor region and serving as a base region; and a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided in the third semiconductor region and serving as an emitter region, wherein the first and second semiconductor regions have an impurity-concentration profile set such that a depletion layer formed in the collector region reaches the semiconductor region when a potential difference between the base region and the emitter region is substantially equal to a potential difference between the collector region and the emitter region.
According to the semiconductor device so constituted, in a bipolar transistor including a high-impurity-concentration region in a collector region and a low-impurity-concentration region contacting a base region, an impurity-concentration profile is set such that a depletion layer formed in the collector region reaches the high-impurity-concentration region when a base-to-emitter voltage Vbe is almost equal to a collector-to-emitter voltage Vce or a base-to-collector voltage Vbc is almost OV. With this structure, too, the same advantage as that of the semiconductor device according to the first aspect can be obtained.
A semiconductor device according to a third aspect of the present invention comprises a first semiconductor region of a first conductivity type, the first semiconductor region serving as a collector region; a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region and serving as a collector region whose impurity concentration is lower than that of the first semiconductor region; a third semiconductor region of a second conductivity type, the third semiconductor region being provided in the second semiconductor region and serving as a base region; and a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided in the third semiconductor region and serving as an emitter region, wherein the second semiconductor region is thinner than a depletion layer formed in the collector region when a potential difference between the base region and the emitter region is substantially equal to a potential difference between the collector region and the emitter region, and the second semiconductor region has an impurity-concentration profile set such that impurity concentration increases in a depth direction.
According to the semiconductor device so constituted, an impurity-concentration profile is set such that the impurity concentration of the low-impurity-concentration collector of the bipolar transistor increases in the depth direction. The same advantages as those of the semiconductor devices according to the above first and second aspects can be obtained.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.